Я не могу заставить работать карты rom и портов. У меня есть разные модули, и я получаю множество ошибок из моего кода. Мой код должен выполнить несколько действий:
1) проверить, нажата ли кнопка на цифровой клавиатуре (цифры от 0 до 9)
2) запомнить эту последовательность
3) проверить правильность (сравнивая входную последовательность с последовательностью, содержащейся в ПЗУ)
4) открыть дверь (открыть <= '1') </p>
-- Module Name: door_lock - Behavioral
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity door_lock is
Port ( badgeSx : in STD_LOGIC;
badgeDx : in STD_LOGIC;
col : in std_logic_vector (0 to 2);
row : in std_logic_vector (0 to 3);
clk : in std_logic;
rst : in std_logic;
unlock : out STD_LOGIC
);
end door_lock;
architecture Behavioral of door_lock is
type state is (locked, c1, c2, c3, c4, unlocked);
signal current_state,next_state : state;
signal badge : std_logic_vector(1 downto 0);
signal attempt : std_logic;
signal wrong : std_logic;
signal attempt_counter : integer range 0 to 3;
signal wrong_counter : integer range 0 to 3;
signal keypressed : std_logic;
signal check : std_logic;
signal temp : std_logic;
type t_vector is array (0 to 3) of integer;
signal vector : t_vector;
type t_temp is array (0 to 3) of integer;
signal int : t_temp;
signal data : integer range 0 to 3;
signal w : std_logic;
signal address : integer range 0 to 9;
signal output : integer range 0 to 9;
signal value : integer range 0 to 9;
component keyboard port (
col : in std_logic_vector (0 to 2);
row : in std_logic_vector (0 to 3);
clk : in std_logic;
rst : in std_logic;
key : out STD_LOGIC
);
end component;
component rom port (
address: in integer range 0 to 3; -- address input
data_out: out integer range 0 to 3 -- data output
);
end component;
component user_memory port (
address : in integer range 0 to 3;
data_in : in integer range 0 to 9;
w : std_logic;
data_out: out integer range 0 to 9
);
end component;
begin
input : keyboard port map (col,row,clk,rst,keypressed);
memory : rom port map (address,data);
user : user_memory port map (attempt_counter,value,w,output);
badge <= badgeDx & badgeSx; --concatenazione dei badge
current_state_register: process(clk) --start
begin
if rising_edge(clk) then
if (rst = '1') then
current_state <= locked;
else
current_state <= next_state;
end if;
end if;
end process;
process (attempt,attempt_counter,wrong,wrong_counter) --counter attempts + wrong attempts
begin
if (attempt = '1') then
attempt_counter <= attempt_counter + 1;
if (wrong = '1') then
wrong_counter <= wrong_counter + 1;
else
wrong_counter <= wrong_counter + 0;
end if;
else
attempt_counter <= attempt_counter + 0;
end if;
end process;
process (col,row,attempt_counter,w,vector) -- row and col to integer
begin
w <= '1';
if (row = "0001") then
if ( col = "001") then
vector(attempt_counter) <= 1;
elsif ( col = "010") then
vector(attempt_counter) <= 2;
elsif (col = "100") then
vector(attempt_counter) <= 3;
end if;
elsif ( row = "0010") then
if ( col = "001") then
vector(attempt_counter) <= 4;
elsif ( col = "010") then
vector(attempt_counter) <= 5;
elsif (col = "100") then
vector(attempt_counter) <= 6;
end if;
elsif ( row = "0011") then
if ( col = "001") then
vector(attempt_counter) <= 7;
elsif ( col = "010") then
vector(attempt_counter) <= 8;
elsif (col = "100") then
vector(attempt_counter) <= 9;
end if;
elsif ((col = "010" or col = "001" or col = "100") and row = "0100") then
vector(attempt_counter) <= 0;
end if;
value <= vector (attempt_counter);
end process;
process (int,address,data)
begin
for address in 0 to 3 loop
int(address) <= data;
end loop;
end process;
process (check,vector,int)
begin
if ((int(0)=vector(0)) and (int(1)=vector(1)) and (int(2)=vector(2)) and (int(3)=vector(3))) then
check <= '1';
else
check <= '0';
end if;
end process;
process (current_state,badge,col,row,keypressed,check) -- macchina sequenziale a stati finiti
begin
case current_state is
when locked =>
unlock <= '0';
attempt <= '0';
if (badge = "01" and keypressed = '0') then
next_state <= c1;
else
next_state <= locked;
end if;
when c1 =>
unlock <= '0';
if ((badge = "00" or badge = "01") and keypressed = '1') then
attempt <= '1';
next_state <= c2;
elsif (badge = "10") then
next_state <= locked;
end if;
when c2 =>
unlock <= '0';
if ((badge = "00" or badge = "01") and keypressed = '1') then
attempt <= '1';
next_state <= c3;
elsif (badge = "10") then
next_state <= locked;
end if;
when c3 =>
unlock <= '0';
if ((badge = "00" or badge = "01") and keypressed = '1') then
attempt <= '1';
next_state <= c4;
elsif (badge = "10") then
next_state <= locked;
end if;
when c4 =>
unlock <= '0';
if ((badge = "00" or badge = "01") and keypressed = '1') then
attempt <= '1';
if (check = '1') then
next_state <= unlocked;
else
next_state <= c1;
end if;
elsif (badge = "10") then
next_state <= locked;
end if;
when unlocked =>
unlock <= '1';
if (badge = "10" and keypressed = '0') then
next_state <= locked;
else
next_state <= unlocked;
end if;
end case;
end process;
end Behavioral;
-- Module Name: keyboard - Behavioral
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.NUMERIC_STD.ALL;
entity keyboard is
port (
col : in std_logic_vector (0 to 2);
row : in std_logic_vector (0 to 3);
clk : in std_logic;
rst : in std_logic;
key : out STD_LOGIC
);
end keyboard;
architecture Behavioral of keyboard is
type state is (notpressed, pressed, released);
signal current_state,next_state : state;
signal k : std_logic;
begin
current_state_register: process(clk)
begin
if rising_edge(clk) then
if (rst = '1') then
current_state <= notpressed;
else
current_state <= next_state;
end if;
end if;
end process;
process (current_state,k,col,row)
begin
case current_state is
when notpressed =>
key <= '0';
if (col /= "000" and row /= "0000") then
k <= '1';
else
k <= '0';
end if;
if (k = '1') then
next_state <= pressed;
else
next_state <= notpressed;
end if;
when pressed =>
key <= '0';
if (col /= "000" and row /= "0000") then
k <= '1';
else
k <= '0';
end if;
if (k = '0') then
next_state <= released;
else
next_state <= pressed;
end if;
when released =>
key <= '1';
k <= '0';
next_state <= notpressed;
end case;
end process;
end Behavioral;
-- Module Name: rom - Behavioral
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity rom is port (
address: in integer range 0 to 3; -- address input
data_out: out integer range 0 to 3); -- data output
end ROM;
architecture BEHAVIOR of ROM is
type rom_table is array (0 to 3) of integer range 0 to 9; --
internal table
constant rom_data : rom_table := (
0 => 1,
1 => 1,
2 => 1,
3 => 1);
begin
process (address)
begin
case address is
when 0 => data_out <= rom_data(0);
when 1 => data_out <= rom_data(1);
when 2 => data_out <= rom_data(2);
when 3 => data_out <= rom_data(3);
end case;
end process;
end BEHAVIOR;
-- Module Name: user_memory - Behavioral
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity user_memory is
port (
address : in integer range 0 to 3;
data_in : in integer range 0 to 9;
w : std_logic;
data_out: out integer range 0 to 9); -- data output
end user_memory;
architecture Behavioral of user_memory is
signal temp : integer range 0 to 9;
type rom_table is array (0 to 3) of integer range 0 to 9; --
internal table
signal rom_data : rom_table ;
begin
process (address,w,data_in,rom_data)
begin
if (w = '1') then
rom_data(address) <= data_in;
else
case address is
when 0 => data_out <= rom_data(0);
when 1 => data_out <= rom_data(1);
when 2 => data_out <= rom_data(2);
when 3 => data_out <= rom_data(3);
end case;
end if;
end process;
end Behavioral;
unlock <= '1', если код верен, в противном случае <= '0', но схема rtl не работает, так как она говорит, что существует множество защелок, и большинство массивов и вектор получают константу 0 </p>
ошибка ошибка