Я новичок в VHDL и пытаюсь внедрить CMOS CD4543 в FPGA basys 3,
и я застрял, потому что я написал 2 модуля, и вывод остается U, и этот вывод должен быть введен во второй модуль. Я сделал тестовые стенды для них обоих и по отдельности они работают corect. Я поставлю код здесь, чтобы увидеть, что не так. Спасибо!
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity latch is
Port ( datain : in STD_LOGIC_VECTOR (3 downto 0);
load : in STD_LOGIC;
data_out : out STD_LOGIC_VECTOR(3 downto 0));
end latch;
architecture Behavioral of latch is
signal data : std_logic_vector (3 downto 0);
Begin
data <= datain when (load = '1') else data;
data_out <= data;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity to7segments is
Port ( datain : in STD_LOGIC_VECTOR (3 downto 0);
bl :in std_logic;
ph :in std_logic;
seg : out STD_LOGIC_VECTOR (6 downto 0);
an : out STD_LOGIC_VECTOR (3 downto 0));
end to7segments;
architecture behavioral of to7segments is
signal data: std_logic_vector(3 downto 0);
Begin
an<="1110";
decoder: process(bl,ph)
begin
if bl= '0' then
if ph ='1' then
data <= not(datain);
end if;
data<=datain;
case data is
when "0000" => seg <="0000001" ;
when "0001" => seg <= "1001111" ;
when "0010" => seg <= "0010010" ;
when "0011" => seg <= "0000110" ;
when "0100" => seg <= "1001100" ;
when "0101" => seg <= "0100100" ;
when "0110" => seg <= "0100000" ;
when "0111" => seg <= "0001111" ;
when "1000" => seg <= "0000000" ;
when "1001" => seg <= "0000100" ;
when "1010" => seg <= "0001000" ;
when "1011" => seg <= "1100000" ;
when "1100" => seg <= "0110001" ;
when "1101" => seg <= "1000010" ;
when "1110" => seg <= "0110000" ;
when "1111" => seg <= "0111000" ;
when others => seg <= "1111111" ;
end case;
elsif bl='1' then
seg<="1111111";
end if;
end process decoder;
end behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity top is
Port ( load : in STD_LOGIC;
ph : in STD_LOGIC;
bl : in STD_LOGIC;
datain :in std_logic_vector( 3 downto 0);
seg : out STD_LOGIC_VECTOR (6 downto 0);
an : out STD_LOGIC_VECTOR (3 downto 0));
end top;
architecture behavioral of top is
component latch PORT ( datain : in STD_LOGIC_VECTOR (3 downto 0);
load : in STD_LOGIC;
data_out : out STD_LOGIC_VECTOR(3 downto 0));
end component;
component to7segments PORT ( datain : inout STD_LOGIC_VECTOR (3 downto 0);
bl :in std_logic;
ph :in std_logic;
seg : out STD_LOGIC_VECTOR (6 downto 0);
an : out STD_LOGIC_VECTOR (3 downto 0));
end component;
signal datain2 : std_logic_vector(3 downto 0);
begin
latch1: latch PORT MAP(datain=>datain,
load =>load,
data_out=>datain2);
decoder: to7segments PORT MAP(datain=>datain2,
bl=>bl,
ph=>ph,
seg=>seg,
an=>an);
end behavioral;