Размер цели VHDL

Question

У меня проблема с заданием, и я не могу ее решить.В этой части кода:

KS1 <= regA when Y(5)='0' else 
                  not regA(0) & not regA(0) & regA(1 to 3) & "000" when (Y(5)='1' and regA(0)='1') else
                  (not(regA(0) & regA) +'1') & "000";

ОШИБКА

ОШИБКА: В процессе OperationUnit.vhd: 94
Целевой размер 8 и исходный размер 12для размера массива 0 не совпадает.

library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_unsigned.ALL;


    entity OperationUnit is
        Port ( clk : in  STD_LOGIC;
               reset : in  STD_LOGIC;
               A : in  STD_LOGIC_VECTOR (0 to 7);
               B : in  STD_LOGIC_VECTOR (0 to 3);
               Y : in  STD_LOGIC_VECTOR (1 to 11);
               R : out  STD_LOGIC_VECTOR (0 to 7);
               P : out  STD_LOGIC_VECTOR (0 to 1);
               F : out  STD_LOGIC_VECTOR (0 to 2));
    end OperationUnit;

    architecture OperationUnit_arch of OperationUnit is

        signal regA : std_logic_vector(0 to 7); -- Register А
        signal regB : std_logic_vector(0 to 3); -- Register В

        signal regR : std_logic_vector(0 to 7) := (others => '0'); -- Register Result, fill zeros.
        signal regP : std_logic_vector(0 to 1); -- Register of type of result


        signal KS1 : std_logic_vector(0 to 7);
        signal KS2 : std_logic_vector(0 to 7);
        signal KS3 : std_logic_vector(0 to 7);
        signal SM : std_logic_vector(0 to 8) := (others => '0'); -- sum
        signal KS4 : std_logic_vector(0 to 7);

    begin


        regA_p : process(clk) -- process register A starting with change clock.
        begin
            if clk' event and clk = '1' then
                if reset = '1' then -- reset synchronous
                    regA <= "00000000";
                else
                    if Y(1) = '1' then
                        regA <= A & "0000";
                    elsif Y(2) = '1' then
                        regA<= regA(0) & '0' & regA(1 to 6);
                    end if;
                end if;
            end if;
        end process regA_p;


        regB_p : process(clk) -- process register B starting with change clock.
        begin
            if clk' event and clk = '1' then
                if reset = '1' then -- reset synchronous
                    regB <= "0000";
                else
                    if Y(3) = '1' then
                        regB <= B;
                    elsif Y(4) = '1' then
                        regB <= regB(0) & regB(2 to 3) & regB(0);
                    end if;
                end if;
            end if;
        end process regB_p;


        KS1 <= regA when Y(5)='0' else 
                  not regA(0) & not regA(0) & regA(1 to 3) & "000" when (Y(5)='1' and regA(0)='1') else
                  (not(regA(0) & regA) +'1') & "000";

        KS2 <= regA when Y(6)='0' else "00000000";

        KS3 <= regR when Y(7)='0' else 
                 regB(0) & regB(0) & regB(1 to 3) & "000" when (Y(7)='1' and regB(0)='0') else
                 regB(0) & regB(0) & (not(regB(1 to 3)) + '1');

        SM <= (('0' & KS1) + ('0' & KS2) + SM(0)) after 1 ns;

        KS4 <= (regA(0) xor regB(0)) & SM(2 to 8) when Y(8)='0' else 
                 SM(1) & 
                 ((SM(5) and (not SM(3))) or
                 (SM(4) and (not SM(3)))or
                 (SM(3) and (not SM(4)) and (not SM(5)))) & 
                 ((SM(4) and (not SM(5))) or (SM(5) and (not SM(4)))) & SM(5) & "0000" when (Y(8)='1' and SM(1)='1') else
                 SM(1) & SM(3 to 5) & "0000";

        regR_p : process(clk) -- process register R starting with change clock.
        begin
            if clk' event and clk = '1' then
                if reset = '1' then -- reset synchronous
                    regR <= x"00";
                else
                    case Y(9 to 10) is
                        when "01" => -- load
                        regR <= KS4(0 to 7);
                        when "10" => -- reset
                        regR <= x"00"; 
                        when others => null;
                    end case;
                end if;
            end if;
        end process regR_p;


        regP_p : process(clk) -- process register P starting with change clock.
        begin
            if clk' event and clk = '1' then
                if reset = '1' then -- reset synchronous
                    regP <= "00";
                else
                    if Y(11) = '1' then
                        if SM(3 to 7) = "00000" then
                            regP <= "00";
                        elsif (SM(1 to 2) = "00")and (SM(3 to 5) /= "000") then
                            regP <= "01";
                        elsif (SM(1 to 2) = "11")and (SM(3 to 5) /= "111") then
                            regP <= "10";
                        elsif (SM(1) /= SM(2)) then
                            regP <= "11";
                        end if;
                    end if;
                end if;
            end if;
        end process regP_p;

    R <= regR;
    P <= regP;
    F(0) <= regA(0);
    F(1) <= regB(0);
    F(2) <= regB(1);

    end OperationUnit_arch;

Answer 1

Вам необходимо пройти через размер цели и источника в назначениях, так как есть несоответствие размера нескольких мест, например, присваивать regA в строке 42:

A : in STD_LOGIC_VECTOR (0 to 7);
...
signal regA : std_logic_vector(0 to 7); -- Register А
...
regA <= A & "0000";

Размер цели равен 8бит (signal regA : in std_logic_vector(0 to 7)) и размер источника составляет 8 бит (A : in STD_LOGIC_VECTOR (0 to 7);) + 4 бита ("0000") = 12 бит.

В сборке ISim могут быть некоторые предупреждения обо всех местах снесоответствие размера.