Может кто-нибудь помочь мне выяснить, что не так с моим VHDL-кодом?Вот код:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity main is
port(
--50MHz clock
cp : in std_logic;
--reset signal
reset : in std_logic;
--PS/2 data and clock lines
ps2d, ps2c : in std_logic;
--7-segment display segments
segments : out std_logic_vector (7 downto 0);
--anode control
an : out std_logic_vector (3 downto 0);
--data out to LEDs
dout : out std_logic_vector (7 downto 0)
);
end main;
architecture Behavioral of main is
--data from keyboard entity (scancode)
signal data : std_logic_vector (7 downto 0);
--7 segments of display
signal segReg, segNext : std_logic_vector (6 downto 0);
signal tickDone : std_logic;
begin
--just entity that reads PS/2 keyboard data
--rx_done is tick (20 ns)
S1: entity keyboard port map ( cp => cp, ps2d => ps2d, ps2c => ps2c,
rx_done => tickDone, dout => data);
dout <= data;
an <= "1110";
segments(6 downto 0) <= segReg;
--turn off dot
segments(7) <= '1';
process (cp, reset)
begin
if reset = '1' then
segReg <= (others => '0');
elsif rising_edge (cp) then
segReg <= segNext;
end if;
end process;
process (tickDone, segReg)
begin
segNext <= segReg;
if tickDone = '1' then
if data = x"16" then
--number 1
segNext <= "1001111";
elsif data = x"1E" then
--number 2
segNext <= "0010010";
elsif data = x"26" then
--number 3
segNext <= "0000110";
elsif data = x"25" then
--number 4
segNext <= "1001100";
else
segNext <= "1111111";
end if;
end if;
end process;
end Behavioral;
Когда я пытаюсь синтезировать его / сгенерировать программный файл, я получаю следующие предупреждения:
WARNING:Xst:819 - "C:/VHDL_projekti/PS2K/main.vhd" line 48: The following signals are missing in the process sensitivity list:
WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology.
WARNING:Xst:1710 - FF/Latch <segReg_0> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_1> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_2> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_3> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_4> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_5> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1710 - FF/Latch <segReg_0> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_1> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_2> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_3> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_4> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_5> (without init value) has a constant value of 0 in block <main>.
WARNING:Par:288 - The signal reset_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
WARNING:PhysDesignRules:367 - The signal <reset_IBUF> is incomplete. The signal
Может ли кто-нибудь помочь мне с этим?Я искал код и не вижу ничего плохого, но, очевидно, я делаю что-то не так.
1) «Следующие сигналы отсутствуют в списке чувствительности процесса» Возможно, это ошибка Xilinx ISE?Я не понимаю, зачем мне нужны какие-либо другие сигналы в списке чувствительности процесса в строке 48 ...
2) "Из-за другой подстройки FF / Latch, имеет постоянное значение 0 в кадре" OK,Что я делаю неправильно ?Я вообще не хочу использовать защелки ...
3) "Сигнал reset_IBUF не загружен. PAR не будет пытаться направить этот сигнал." Что это значит?Что не так с моим сигналом сброса?Почему он неполный?
Этот код является моей попыткой использования клавиатуры PS / 2 со стартовой платой Spartan 3.«Клавиатура» объекта выполняет считывание и работает правильно (когда я тестирую ее в одиночку, я получаю правильные коды сканирования по сигналу dout (я вижу это на светодиодах)).rx_done - это тик (20 нс), который сигнализирует, что скан-код был успешно прочитан.
Поэтому я просто хотел посмотреть, смогу ли я как-то распознать коды сканирования (во втором процессе я сравниваю сигнал данных и выставляю правильные значениясигнал segNext) и отображать что-то на 7-сегментном дисплее.Когда я заставлю это работать, я реализую правильное поведение (обнаружение всех кодов сканирования, дополнительных клавиш и событий нажатия клавиш и нажатия клавиш).
Я не уверен, нужно ли мне что-либо описыватьиначе, если я сделаю это, пожалуйста, оставьте мне комментарий:)
Спасибо за вашу помощь !!!!
EDIT: отредактированный код (добавлены данные в список чувствительности и еще в условие if)):
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity main is
port(
--50MHz clock
cp : in std_logic;
--reset signal
reset : in std_logic;
--PS/2 data and clock lines
ps2d, ps2c : in std_logic;
--7-segment display segments
segments : out std_logic_vector (7 downto 0);
--anode control
an : out std_logic_vector (3 downto 0);
--data out to LEDs
dout : out std_logic_vector (7 downto 0)
);
end main;
architecture Behavioral of main is
--data from keyboard entity (scancode)
signal data : std_logic_vector (7 downto 0);
--7 segments of display
signal segReg, segNext : std_logic_vector (6 downto 0);
signal tickDone : std_logic;
begin
--just entity that reads PS/2 keyboard data
--rx_done is tick (20 ns)
S1: entity keyboard port map ( cp => cp, ps2d => ps2d, ps2c => ps2c,
rx_done => tickDone, dout => data);
dout <= data;
an <= "1110";
segments(6 downto 0) <= segReg;
--turn off dot
segments(7) <= '1';
process (cp, reset)
begin
if reset = '1' then
segReg <= (others => '0');
elsif rising_edge (cp) then
segReg <= segNext;
end if;
end process;
process (tickDone, segReg, data)
begin
if tickDone = '1' then
if data = x"16" then
--number 1
segNext <= "1001111";
elsif data = x"1E" then
--number 2
segNext <= "0010010";
elsif data = x"26" then
--number 3
segNext <= "0000110";
elsif data = x"25" then
--number 4
segNext <= "1001100";
else
segNext <= "1111111";
end if;
else
segNext <= segReg;
end if;
end process;
end Behavioral;
К сожалению, после этих правок у меня все еще есть следующие предупреждения:
WARNING:Xst:1710 - FF/Latch <segReg_0> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_1> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_2> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_3> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_4> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_5> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_6> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <segReg_0> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_1> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_2> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_3> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_4> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_5> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Par:288 - The signal reset_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.