Синхронизация двух компонентов для фильтрации изображения

Question

У меня есть компонент для чтения полутонового изображения из текстового файла (значения пикселей) и компонент, состоящий из сдвигового регистра, который выполняет некоторые операции над считанными данными. Оба компонента работают при тестировании по отдельности, но когда я пытаюсь соединить их, моя симуляция застревает на 0 фс. У кого-нибудь есть идеи, в чем может быть проблема?

Мой код указан ниже.

library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use work.pkg.all;


entity main is
    port (
        rstb:       in  std_logic;
        clk:        in  std_logic;
        en:         in std_logic;
        row:        out integer;
        col:        out integer;
        last_elem:  out integer;
        output_Data:out matrixData
    );
end entity main;

architecture behavioral of main is
    --type matrixdata is array (0 to 240, 0 to 217) of integer;
    --type matrixdata is array (0 to 3, 0 to 2) of integer;
    signal data:    matrixdata;
    signal data2:    matrixdata;
    signal test:    integer;

begin
    process
        file read_file:         text;
        variable file_line:     line;
        variable row_counter:   integer := 0;
        variable rows:          integer;
        variable cols:          integer;
        variable read_value:    integer;
        variable open_status:   FILE_OPEN_STATUS; -- ADDED
    begin
        if (en='1') then
        file_open(open_status,read_file, "f:\faculta\an 3 sem 2\scs\image.txt", read_mode);


        case open_status is  -- ADDED
             when OPEN_OK =>
                report "read_file opened for read" severity NOTE;
        when STATUS_ERROR =>
            report "read_file already open" severity FAILURE;
        when NAME_ERROR =>
            report "read_file file name not found" severity FAILURE;
        when MODE_ERROR =>
            report "read_file can't be opened for read" severity FAILURE;
    end case;

    if endfile(read_file) then  -- ADDED
        report "can't read first line from read_file"
        severity FAILURE;
    end if;
    readline (read_file, file_line);
    read (file_line, rows);
    read (file_line, cols);
    row <= rows;
    col <= cols;

    for i in 0 to rows - 1 loop
        if endfile(read_file) then   -- ADDED
            report "can't read line for all rows from read_file"
            severity FAILURE;
        end if;
        readline (read_file, file_line);
        for j in 0 to cols - 1 loop
                read(file_line, read_value);
                data(i,j) <= read_value;
        end loop;
    end loop;

    wait for 0 ns;  --  ADDED causes a delta cycle, data is updated
    test <= data(0, 0);
    wait for 0 ns;  -- ADDED causes a delta cycle, test is updated
    last_elem <= test;

    wait for 0 ns;
   output_Data<=data;


    file_close(read_file);
    wait;           -- ADDED

    end if;
end process;

end behavioral;

Регистр

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.pkg.all;



entity shift_reg is
port(
clk:in std_logic;
reset:in std_logic;
input:in integer;
q:out int_vector;
iter:out integer
);

end shift_reg;

architecture Behavioral of shift_reg is

signal state:int_vector;
signal iteration:integer:=0;
begin
    process(clk)
    begin
    if (reset='1') then 
    state<=(0,others=>0);
    elsif (clk'event and clk='1') then
    iteration<=iteration+1;

    state(5 downto 1)<= state(4 downto 0);
    state(0)<=input;
        if (iteration>2) then
        state(3)<=state(2)+state(1)+state(0);
        end if;
    end if;
    q<=state;
    iter<=iteration;
    end process;
end Behavioral;

Некоторые типы данных

library ieee;
use ieee.std_logic_1164.all;

package pkg is
  type matrixdata is array (0 to 240, 0 to 217) of integer;
  type int_vector is array (52537 downto 0) of integer;
end package;

package body pkg is
end package body;

Тестовый стенд, на котором я пытаюсь их подключить:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.pkg.all;

entity porting is
--  Port ( );
end porting;

architecture Behavioral of porting is
component main is
   port (
        rstb:       in  std_logic;
        clk:        in  std_logic;
        en:         in std_logic;
        row:        out integer;
        col:        out integer;
        last_elem:  out integer;
        output_Data:out matrixData
    );
end component;

component shift_reg is
port(
clk:in std_logic;
reset:in std_logic;
input:in integer;
q:out int_vector;
iter:out integer
);

end component;
signal data:matrixData;
signal row1: integer;
signal col1:integer;
signal element:integer;
signal clk:std_logic:='0';
signal enable:std_logic:='0';
signal reset:std_logic:='0';
signal input_elem:integer;
signal output_data:int_vector;
signal iteration: integer;
constant clk_period: time:=10 ns;
begin

p1: main port map('0','1',enable,row1,col1,element,data);

p2: shift_reg port map(clk,'0',input_elem,output_data,iteration);

clk_process :process
      variable state:integer:=0;
      variable r,c:integer;
      begin
          state:=state+1;
          c:=state mod col1;
          r:=state/col1;
          input_elem<=data(r,c);
          clk <= '0';
          wait for clk_period/2;
          clk <= '1';
          wait for clk_period/2;
      end process;

enable_process:process
    begin
        enable<='1';
        wait for clk_period*52538;
        enable<='0';

    end process;
end Behavioral;