чем отличаются форматы сигналов в systemC?

Question

В приведенной ниже ссылке я изменил входной файл в строке 26 с vcd на wif, но получил эту ошибку:

"No *.vcd file found. EPWave will not open. Did you use '$dumpfile("dump.vcd"); $dumpvars;'?"

Я хотел бы знать, почему это происходит и как я могу изменить форматы файлов сигналов.

Каковы различия между этими форматами файлов, которые вызывают такую ​​ошибку? Буду признателен, если вы немного расскажете о файлах трассировки.

https://www.edaplayground.com/x/5kG9

EDIT:

это код:

//-----------------------------------------------------
// A 4 bit up-counter with synchronous active high reset
// and with active high enable signal
// Example from www.asic-world.com
//-----------------------------------------------------
#include "systemc.h"

SC_MODULE (first_counter) {
  sc_in_clk     clock ;      // Clock input of the design
  sc_in<bool>   reset ;      // active high, synchronous Reset input
  sc_in<bool>   enable;      // Active high enable signal for counter
  sc_out<sc_uint<4> > counter_out; // 4 bit vector output of the counter

  //------------Local Variables Here---------------------
  sc_uint<4>    count;
//sc_clock mclk(“mclk”,20,0.3,7,false);
  //------------Code Starts Here-------------------------
  // Below function implements actual counter logic
  void incr_count () {
      //sc_clock clk(“mclk”,20,0.3,7,false);
    // At every rising edge of clock we check if reset is active
    // If active, we load the counter output with 4'b0000
    while (1){
       wait();
    if (reset.read() == 1) {
      count =  5;
      counter_out.write(count);
    // If enable is active, then we increment the counter
    } else if (enable.read() == 1) {
      count = count + 1;
      counter_out.write(count);
      cout<<"@" << sc_time_stamp() <<" :: Incremented Counter "
        <<counter_out.read()<<endl;
    }

    }// end of while
  } // End of function incr_count

  // Constructor for the counter
  // Since this counter is a positive edge trigged one,
  // We trigger the below block with respect to positive
  // edge of the clock and also when ever reset changes state
 SC_CTOR(first_counter) {
    cout<<"Executing new"<<endl;
   // SC_METHOD(incr_count);
   SC_CTHREAD(incr_count,clock.pos());
  //  sensitive << reset<<clock.pos();
//   sensitive(reset);//,clock);
  // sensitive << clock.pos();
  } // End of Constructor

}; // End of Module counter

а это тестовый стенд:

//-----------------------------------------------------
// Testbench for the 4-bit up-counter ---------------->
// Example from www.asic-world.com (with fixes)
//-----------------------------------------------------
#include "systemc.h"
#include "design.cpp"

int sc_main (int argc, char* argv[]) {
  sc_signal<bool>   clock;
  sc_signal<bool>   reset;
  sc_signal<bool>   enable;
  sc_signal<sc_uint<4> > counter_out;
  //sc_signal mclk;
  int i = 0;
  // Connect the DUT
  first_counter counter("COUNTER");
  counter.clock(clock);
  counter.reset(reset);
  counter.enable(enable);
  counter.counter_out(counter_out);

  sc_clock mclk("mclk",20,0.3,7,false);

  sc_start(1, SC_NS);
  // Open VCD file
  sc_trace_file *wf = sc_create_vcd_trace_file("counter");
  // Dump the desired signals
  sc_trace(wf, clock, "clock");
  sc_trace(wf, reset, "reset");
  sc_trace(wf, enable, "enable");
  sc_trace(wf, counter_out, "count");
  //sc_trace(wf, mclk, "mclk");

  // Initialize all variables
  reset = 0;       // initial value of reset
  enable = 0;      // initial value of enable
  for (i=0;i<5;i++) {
    clock = 0; 
    sc_start(1, SC_NS);
    clock = 1; 
    sc_start(1, SC_NS);
  }
  reset = 1;    // Assert the reset
  cout << "@" << sc_time_stamp() <<" Asserting reset\n" << endl;
  for (i=0;i<10;i++) {
    clock = 0; 
    sc_start(1, SC_NS);
    clock = 1; 
    sc_start(1, SC_NS);
  }
  reset = 0;    // De-assert the reset
  cout << "@" << sc_time_stamp() <<" De-Asserting reset\n" << endl;
  for (i=0;i<5;i++) {
    clock = 0; 
    sc_start(1, SC_NS);
    clock = 1; 
    sc_start(1, SC_NS);
  }
  cout << "@" << sc_time_stamp() <<" Asserting Enable\n" << endl;
  enable = 1;  // Assert enable
  for (i=0;i<20;i++) {
    clock = 0; 
    sc_start(1, SC_NS);
    clock = 1; 
    sc_start(1, SC_NS);
  }
  cout << "@" << sc_time_stamp() <<" De-Asserting Enable\n" << endl;
  enable = 0; // De-assert enable

  cout << "@" << sc_time_stamp() <<" Terminating simulation\n" << endl;
  sc_close_vcd_trace_file(wf);
  return 0;// Terminate simulation

}