Я получаю эту ошибку, когда пытаюсь выполнить симуляцию после синтеза на своем стенде в Vviado.
Я проверял снова и снова, и я не могу обнаружить никакого несоответствия, плюс один и тот же код прекрасно работал для моделирования поведения, sendhesis и реализации.
PS: Testbench - это не мой код, но я пытаюсь сгенерировать SAIF-файлы для проекта.
полная ошибка:
[VRFC 10-718] formal port <Out_block_3> does not exist in entity <\CNN_Network\>. Please compare the definition of block <\CNN_Network\> to its component declaration and its instantion to detect the mismatch. ["C:/matlab2/Isesimulation/3 Blocks_subsystems/hdlsrc/CNNSimulink_Blocks/CNN_Network_tb.vhd":69]
Верхний модуль
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.CNN_Network_pkg.ALL;
ENTITY CNN_Network IS
PORT( clk : IN std_logic;
reset : IN std_logic;
clk_enable : IN std_logic;
In1 : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En4
In2_hStart : IN std_logic;
In2_hEnd : IN std_logic;
In2_vStart : IN std_logic;
In2_vEnd : IN std_logic;
In2_valid : IN std_logic;
ce_out : OUT std_logic;
Out_block_3 : OUT vector_of_std_logic_vector16(0 TO 9); -- ufix16_En12 [10]
Out_Block1 : OUT vector_of_std_logic_vector16(0 TO 9); -- ufix16_En12 [10]
Out_Block2 : OUT vector_of_std_logic_vector16(0 TO 9) -- ufix16_En12 [10]
);
END CNN_Network;
ARCHITECTURE rtl OF CNN_Network IS
-- Component Declarations
COMPONENT Subsystem2
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
In1 : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
In2_hStart : IN std_logic;
In2_hEnd : IN std_logic;
In2_vStart : IN std_logic;
In2_vEnd : IN std_logic;
In2_valid : IN std_logic;
Out1 : OUT vector_of_std_logic_vector16(0 TO 9); -- ufix16_En12 [10]
Out2 : OUT vector_of_std_logic_vector16(0 TO 7); -- ufix16_En15 [8]
Out3_hStart : OUT std_logic;
Out3_hEnd : OUT std_logic;
Out3_vStart : OUT std_logic;
Out3_vEnd : OUT std_logic;
Out3_valid : OUT std_logic
);
END COMPONENT;
COMPONENT Subsystem1
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
In1 : IN vector_of_std_logic_vector16(0 TO 7); -- ufix16_En15 [8]
In2_hStart : IN std_logic;
In2_hEnd : IN std_logic;
In2_vStart : IN std_logic;
In2_vEnd : IN std_logic;
In2_valid : IN std_logic;
Out1 : OUT vector_of_std_logic_vector16(0 TO 9); -- ufix16_En12 [10]
Out2 : OUT vector_of_std_logic_vector16(0 TO 7); -- ufix16_En15 [8]
Out3_hStart : OUT std_logic;
Out3_hEnd : OUT std_logic;
Out3_vStart : OUT std_logic;
Out3_vEnd : OUT std_logic;
Out3_valid : OUT std_logic
);
END COMPONENT;
COMPONENT Subsystem
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
In1 : IN vector_of_std_logic_vector16(0 TO 7); -- ufix16_En15 [8]
In2_hStart : IN std_logic;
In2_hEnd : IN std_logic;
In2_vStart : IN std_logic;
In2_vEnd : IN std_logic;
In2_valid : IN std_logic;
Out1 : OUT vector_of_std_logic_vector16(0 TO 9) -- ufix16_En12 [10]
);
END COMPONENT;
-- Component Configuration Statements
FOR ALL : Subsystem2
USE ENTITY work.Subsystem2(rtl);
FOR ALL : Subsystem1
USE ENTITY work.Subsystem1(rtl);
FOR ALL : Subsystem
USE ENTITY work.Subsystem(rtl);
-- Signals
SIGNAL In1_signed : signed(15 DOWNTO 0); -- sfix16_En4
SIGNAL Data_Type_Conversion2_out1 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL Subsystem2_out1 : vector_of_std_logic_vector16(0 TO 9); -- ufix16 [10]
SIGNAL Subsystem2_out2 : vector_of_std_logic_vector16(0 TO 7); -- ufix16 [8]
SIGNAL Subsystem2_out3_hStart : std_logic;
SIGNAL Subsystem2_out3_hEnd : std_logic;
SIGNAL Subsystem2_out3_vStart : std_logic;
SIGNAL Subsystem2_out3_vEnd : std_logic;
SIGNAL Subsystem2_out3_valid : std_logic;
SIGNAL Subsystem1_out1 : vector_of_std_logic_vector16(0 TO 9); -- ufix16 [10]
SIGNAL Subsystem1_out2 : vector_of_std_logic_vector16(0 TO 7); -- ufix16 [8]
SIGNAL Subsystem1_out3_hStart : std_logic;
SIGNAL Subsystem1_out3_hEnd : std_logic;
SIGNAL Subsystem1_out3_vStart : std_logic;
SIGNAL Subsystem1_out3_vEnd : std_logic;
SIGNAL Subsystem1_out3_valid : std_logic;
SIGNAL Subsystem_out1 : vector_of_std_logic_vector16(0 TO 9); -- ufix16 [10]
BEGIN
u_Subsystem2 : Subsystem2
PORT MAP( clk => clk,
reset => reset,
enb => clk_enable,
In1 => std_logic_vector(Data_Type_Conversion2_out1), -- sfix16_En13
In2_hStart => In2_hStart,
In2_hEnd => In2_hEnd,
In2_vStart => In2_vStart,
In2_vEnd => In2_vEnd,
In2_valid => In2_valid,
Out1 => Subsystem2_out1, -- ufix16_En12 [10]
Out2 => Subsystem2_out2, -- ufix16_En15 [8]
Out3_hStart => Subsystem2_out3_hStart,
Out3_hEnd => Subsystem2_out3_hEnd,
Out3_vStart => Subsystem2_out3_vStart,
Out3_vEnd => Subsystem2_out3_vEnd,
Out3_valid => Subsystem2_out3_valid
);
u_Subsystem1 : Subsystem1
PORT MAP( clk => clk,
reset => reset,
enb => clk_enable,
In1 => Subsystem2_out2, -- ufix16_En15 [8]
In2_hStart => Subsystem2_out3_hStart,
In2_hEnd => Subsystem2_out3_hEnd,
In2_vStart => Subsystem2_out3_vStart,
In2_vEnd => Subsystem2_out3_vEnd,
In2_valid => Subsystem2_out3_valid,
Out1 => Subsystem1_out1, -- ufix16_En12 [10]
Out2 => Subsystem1_out2, -- ufix16_En15 [8]
Out3_hStart => Subsystem1_out3_hStart,
Out3_hEnd => Subsystem1_out3_hEnd,
Out3_vStart => Subsystem1_out3_vStart,
Out3_vEnd => Subsystem1_out3_vEnd,
Out3_valid => Subsystem1_out3_valid
);
u_Subsystem : Subsystem
PORT MAP( clk => clk,
reset => reset,
enb => clk_enable,
In1 => Subsystem1_out2, -- ufix16_En15 [8]
In2_hStart => Subsystem1_out3_hStart,
In2_hEnd => Subsystem1_out3_hEnd,
In2_vStart => Subsystem1_out3_vStart,
In2_vEnd => Subsystem1_out3_vEnd,
In2_valid => Subsystem1_out3_valid,
Out1 => Subsystem_out1 -- ufix16_En12 [10]
);
In1_signed <= signed(In1);
Data_Type_Conversion2_out1 <= In1_signed(6 DOWNTO 0) & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0';
ce_out <= clk_enable;
Out_block_3 <= Subsystem_out1;
Out_Block1 <= Subsystem2_out1;
Out_Block2 <= Subsystem1_out1;
END rtl;
Часть TestBench
LIBRARY IEEE;
USE IEEE.std_logic_textio.ALL;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
LIBRARY STD;
USE STD.textio.ALL;
LIBRARY work;
USE work.CNN_Network_pkg.ALL;
USE work.CNN_Network_tb_pkg.ALL;
ENTITY CNN_Network_tb IS
PORT( clk : IN std_logic
);
END CNN_Network_tb;
ARCHITECTURE rtl OF CNN_Network_tb IS
-- Component Declarations
COMPONENT CNN_Network
PORT( clk : IN std_logic;
reset : IN std_logic;
clk_enable : IN std_logic;
In1 : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En4
In2_hStart : IN std_logic;
In2_hEnd : IN std_logic;
In2_vStart : IN std_logic;
In2_vEnd : IN std_logic;
In2_valid : IN std_logic;
ce_out : OUT std_logic;
Out_block_3 : OUT vector_of_std_logic_vector16(0 TO 9); -- ufix16_En12 [10]
Out_Block1 : OUT vector_of_std_logic_vector16(0 TO 9); -- ufix16_En12 [10]
Out_Block2 : OUT vector_of_std_logic_vector16(0 TO 9) -- ufix16_En12 [10]
);
END COMPONENT;
-- Component Configuration Statements
FOR ALL : CNN_Network
USE ENTITY work.CNN_Network(rtl);
-- Signals
SIGNAL reset : std_logic;
SIGNAL clk_enable : std_logic;
SIGNAL resetn : std_logic;
SIGNAL Out_Block2_done : std_logic; -- ufix1
SIGNAL rdEnb : std_logic;
SIGNAL Out_Block2_done_enb : std_logic; -- ufix1
SIGNAL Out_block_3_addr : unsigned(10 DOWNTO 0); -- ufix11
SIGNAL Out_Block2_lastAddr : std_logic; -- ufix1
SIGNAL check3_done : std_logic; -- ufix1
SIGNAL Out_Block1_done : std_logic; -- ufix1
SIGNAL Out_Block1_done_enb : std_logic; -- ufix1
SIGNAL Out_Block1_lastAddr : std_logic; -- ufix1
SIGNAL check2_done : std_logic; -- ufix1
SIGNAL Out_block_3_done : std_logic; -- ufix1
SIGNAL Out_block_3_done_enb : std_logic; -- ufix1
SIGNAL Out_block_3_active : std_logic; -- ufix1
SIGNAL Frame_To_Pixels2_out1_addr : unsigned(10 DOWNTO 0); -- ufix11
SIGNAL Frame_To_Pixels2_out2_4_bus_addr_delay_1 : unsigned(10 DOWNTO 0); -- ufix11
SIGNAL tb_enb_delay : std_logic;
SIGNAL rawData_In2_valid : std_logic;
SIGNAL holdData_In2_valid : std_logic;
SIGNAL In2_valid_offset : std_logic;
SIGNAL In2_valid : std_logic;
SIGNAL Frame_To_Pixels2_out2_3_bus_addr_delay_1 : unsigned(10 DOWNTO 0); -- ufix11
SIGNAL rawData_In2_vEnd : std_logic;
SIGNAL holdData_In2_vEnd : std_logic;
SIGNAL In2_vEnd_offset : std_logic;
SIGNAL In2_vEnd : std_logic;
SIGNAL Frame_To_Pixels2_out2_2_bus_addr_delay_1 : unsigned(10 DOWNTO 0); -- ufix11
SIGNAL rawData_In2_vStart : std_logic;
SIGNAL holdData_In2_vStart : std_logic;
SIGNAL In2_vStart_offset : std_logic;
SIGNAL In2_vStart : std_logic;
SIGNAL Frame_To_Pixels2_out2_1_bus_addr_delay_1 : unsigned(10 DOWNTO 0); -- ufix11
SIGNAL rawData_In2_hEnd : std_logic;
SIGNAL holdData_In2_hEnd : std_logic;
SIGNAL In2_hEnd_offset : std_logic;
SIGNAL In2_hEnd : std_logic;
SIGNAL Frame_To_Pixels2_out2_bus_addr_delay_1 : unsigned(10 DOWNTO 0); -- ufix11
SIGNAL rawData_In2_hStart : std_logic;
SIGNAL holdData_In2_hStart : std_logic;
SIGNAL In2_hStart_offset : std_logic;
SIGNAL In2_hStart : std_logic;
SIGNAL Frame_To_Pixels2_out1_active : std_logic; -- ufix1
SIGNAL Frame_To_Pixels2_out1_enb : std_logic; -- ufix1
SIGNAL Frame_To_Pixels2_out1_addr_delay_1 : unsigned(10 DOWNTO 0); -- ufix11
SIGNAL rawData_In1 : signed(15 DOWNTO 0); -- sfix16_En4
SIGNAL holdData_In1 : signed(15 DOWNTO 0); -- sfix16_En4
SIGNAL In1_offset : signed(15 DOWNTO 0); -- sfix16_En4
SIGNAL In1 : signed(15 DOWNTO 0); -- sfix16_En4
SIGNAL In1_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL snkDone : std_logic;
SIGNAL snkDonen : std_logic;
SIGNAL tb_enb : std_logic;
SIGNAL ce_out : std_logic;
SIGNAL Out_block_3 : vector_of_std_logic_vector16(0 TO 9); -- ufix16 [10]
SIGNAL Out_Block1 : vector_of_std_logic_vector16(0 TO 9); -- ufix16 [10]
SIGNAL Out_Block2 : vector_of_std_logic_vector16(0 TO 9); -- ufix16 [10]
SIGNAL Out_block_3_enb : std_logic; -- ufix1
SIGNAL Out_block_3_lastAddr : std_logic; -- ufix1
SIGNAL check1_done : std_logic; -- ufix1
SIGNAL Out_block_3_unsigned : vector_of_unsigned16(0 TO 9); -- ufix16_En12 [10]
SIGNAL Out_block_3_addr_delay_1 : unsigned(10 DOWNTO 0); -- ufix11
SIGNAL Out_block_3_expected : vector_of_unsigned16(0 TO 9); -- ufix16_En12 [10]
SIGNAL Out_block_3_ref : vector_of_unsigned16(0 TO 9); -- ufix16_En12 [10]
SIGNAL Out_block_3_testFailure : std_logic; -- ufix1
SIGNAL Out_Block1_unsigned : vector_of_unsigned16(0 TO 9); -- ufix16_En12 [10]
SIGNAL Out_Block1_addr_delay_1 : unsigned(10 DOWNTO 0); -- ufix11
SIGNAL Out_Block1_expected : vector_of_unsigned16(0 TO 9); -- ufix16_En12 [10]
SIGNAL Out_Block1_ref : vector_of_unsigned16(0 TO 9); -- ufix16_En12 [10]
SIGNAL Out_Block1_testFailure : std_logic; -- ufix1
SIGNAL Out_Block2_unsigned : vector_of_unsigned16(0 TO 9); -- ufix16_En12 [10]
SIGNAL Out_Block2_addr_delay_1 : unsigned(10 DOWNTO 0); -- ufix11
SIGNAL Out_Block2_expected : vector_of_unsigned16(0 TO 9); -- ufix16_En12 [10]
SIGNAL Out_Block2_ref : vector_of_unsigned16(0 TO 9); -- ufix16_En12 [10]
SIGNAL Out_Block2_testFailure : std_logic; -- ufix1
SIGNAL testFailure : std_logic; -- ufix1
BEGIN
u_CNN_Network : CNN_Network
PORT MAP( clk => clk,
reset => reset,
clk_enable => clk_enable,
In1 => In1_1, -- sfix16_En4
In2_hStart => In2_hStart,
In2_hEnd => In2_hEnd,
In2_vStart => In2_vStart,
In2_vEnd => In2_vEnd,
In2_valid => In2_valid,
ce_out => ce_out,
Out_block_3 => Out_block_3, -- ufix16_En12 [10]
Out_Block1 => Out_Block1, -- ufix16_En12 [10]
Out_Block2 => Out_Block2 -- ufix16_En12 [10]
);