Я пытаюсь запустить FSM и Adder в VHDL, чтобы он действовал как торговый автомат, но я получаю некоторые ошибки. Предполагается, что автомат FSM определит, сколько денег вы вложите в автомат иПредполагается, что сумматор добавляет состояния и в конечном итоге дает вам изменения.Вивадо продолжает думать, что мой код является массивом, и я не знаю, почему, кто-нибудь может мне помочь?
Я пытался запустить его и изменить некоторые вещи, но продолжаю получать ошибки.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity vend is
port(
clock, reset, sensor, item: in std_logic;
coin: in std_logic_vector (1 downto 0);
change_done, item_done: out std_logic;
change: out std_logic_vector (1 downto 0);
A : in std_logic;
B : in std_logic;
Cin : in std_logic;
S : out std_logic;
Cout : out std_logic);
end vend;
architecture Behavioral of vend is
type mealy_fsm is (rest, coin_in, in_1, in_2, coin_out, item_out);
signal current_state, next_state: MEALY_FSM;
begin
process(clock,reset)
begin
S <= A XOR B XOR Cin ;
Cout <= (A AND B) OR (Cin AND A) OR (Cin AND B) ;
if(reset = '0')then
current_state <= rest;
elsif(rising_edge(clock))then
current_state <= next_state;
end if;
end process;
process(current_state, coin)
begin
S <= A XOR B XOR Cin ;
Cout <= (A AND B) OR (Cin AND A) OR (Cin AND B) ;
case current_state is
when rest =>
item_done <= '0';
change <= "00";
next_state <= coin_in;
when coin_in =>
if(coin = "00")then
item_done <= '0';
change <= "00";
change_done <= '1';
next_state <= coin_in;
elsif(coin = "01")then
item_done <= '0';
change <= "00";
change_done <= '1';
next_state <= in_1;
elsif(coin = "10")then
item_done <= '0';
change <= "00";
change_done <= '1';
next_state <= in_2;
end if;
S <= A XOR B XOR Cin ;
Cout <= (A AND B) OR (Cin AND A) OR (Cin AND B) ;
when in_1 =>
if(item = '1')then
item_done <= '1';
change <= "00";
change_done <= '1';
next_state <= coin_out;
elsif(coin = "00")then
item_done <= '0';
change <= "00";
change_done <= '1';
next_state <= in_1;
elsif(coin = "01")then
item_done <= '0';
change <= "00";
change_done <= '1';
next_state <= in_2;
end if;
S <= A XOR B XOR Cin ;
Cout <= (A AND B) OR (Cin AND A) OR (Cin AND B) ;
when in_2 =>
if(item = '1')then
item_done <= '1';
change <= "00";
change_done <= '0';
next_state <= coin_out;
elsif(coin = "00")then
item_done <= '0';
change <= "00";
change_done <= '1';
next_state <= in_2;
end if;
end case;
end process;
end Behavioral;
И тестовый стенд:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY vend_tb IS
END vend_tb;
ARCHITECTURE behavior OF vend_tb IS
-- Component Declaration for the Moore FSM Sequence Detector in VHDL
COMPONENT vend
PORT(
clock : IN std_logic;
reset : IN std_logic;
sensor : IN std_logic;
coin : IN std_logic_vector (1 downto 0);
change: out std_logic_vector (1 downto 0);
change_done : OUT std_logic;
A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Cout : out STD_LOGIC);
END COMPONENT;
--Inputs
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal sensor : std_logic := '0';
signal coin : std_logic_vector (1 downto 0) := "00";
signal A : std_logic := '0';
signal B : std_logic := '0';
signal Cin : std_logic := '0';
--Outputs
signal change : std_logic_vector (1 downto 0) := "00";
signal change_done : std_logic;
signal S : std_logic;
signal Cout : std_logic;
-- Clock period definitions
constant clock_period : time := 10 ns;
BEGIN
uut: vend PORT MAP (
clock => clock,
reset => reset,
coin => coin,
sensor => sensor,
change => change,
change_done => change_done,
A => A,
B => B,
Cin => Cin,
S => S,
Cout => Cout
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
sensor <= '0';
reset <= '1';
-- Wait 100 ns for global reset to finish
wait for 30 ns;
reset <= '0';
wait for 40 ns;
sensor <= '1';
wait for 10 ns;
sensor <= '0';
wait for 10 ns;
sensor <= '1';
wait for 20 ns;
sensor <= '0';
wait for 20 ns;
sensor <= '1';
wait for 20 ns;
sensor <= '0';
-- hold reset state for 100 ns.
wait for 100 ns;
-- insert stimulus here
A <= '1';
B <= '0';
Cin <= '0';
wait for 10 ns;
A <= '0';
B <= '1';
Cin <= '0';
wait for 10 ns;
A <= '0';
B <= '0';
Cin <= '1';
wait for 10 ns;
A <= '0';
B <= '0';
Cin <= '0';
wait for 10 ns;
-- insert stimulus here
wait;
end process;
END;
Мой ожидаемый результат должен быть просто сигналом, когда я симулирую код, просто чтобы увидеть, что FSM и Adder работают вместе без каких-либо проблем.
Полученные ошибки:
[VRFC 10-2335] case statement does not cover all choices. 'others' clause is needed [vend.vhd:39]
[VRFC 10-704] formal item has no actual or default value [vend.vhd:6]
[XSIM 43-3321] Static elaboration of top level VHDL design unit vend_tb in library work failed.