коды verilog файла BIST_controller.v
`timescale 10ns/1ns
module BIST_controller();
reg s,clk,rst;
wire [127:0] getValue;
wire z;
integer i;
initial begin
s=1;
clk=0;
rst=0;
#1 rst=1;
end
m21 mu(s,z);
TPG tpg(clk,z,rst,getValue);
always
#1 clk = ~clk;
always @(getValue)begin
$display("%d %b",$time,getValue);
end
endmodule
коды verilog файла m21.v
module m21(input wire s,output reg y);
always @(s)
begin
if(s)
y=1;
else
y=0;
end
endmodule
коды verilog файла TPG.v
module TPG(input wire clk, input wire bistMode,input wire rst, output reg[127:0] getValue);
integer i;
reg [127:0] temp[0:1000];
initial begin
i=1;
getValue=128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
end
always@(posedge clk or negedge rst)begin
if(bistMode == 1)begin
if(!rst)begin
temp[0] = 128'b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
end
else
begin
temp[i] <= {(temp[i-1][127] ^ temp[i-1][126] ^ temp[i-1][125] ^ temp[i-1][120]), temp[i-1][127:1]};
getValue <= temp[i];
i<=i+1;
end
end
end
endmodule