Цель состоит в том, чтобы реализовать последовательную логику c проблемы миссионера и каннибала. - Мне нужно иметь 4 D триггера, которые хранят текущее состояние, и еще один регистр, который хранит направление. Затем комбинационный лог c (модуль мс) миссионера и каннибала « принимает» текущее состояние и направление в качестве входных данных (возможно, использует провод), а затем выводит следующее состояние.
Право теперь у меня есть этот код (ниже): Не совсем уверен, правильно ли я делаю, но я хотел бы знать, как сделать направление logi c и принять его модулем ms. Пожалуйста, помогите ... Код благодарности: Verilog HDL
module missionary_cannibal(clock,reset,missionary_next,cannibal_next, finish);
input clock,reset;
output[1:0] missionary_next;
output[1:0] cannibal_next;
output finish;
DFF3 c2(cannibal_next[1], , clock);
DFF4 c1(cannibal_next[0], , clock);
DFF m2(missionary_next[1], , clock);
DFF2 m1(missionary_next[0], , clock);
ms MC( , , , missionary_next, cannibal_next);
endmodule
module DFF(Q, D, clk, reset);
output reg Q;
input clk,reset;
input wire D;
always @(posedge clk or posedge reset)
if(reset) Q <= 1'b0;
else Q <= D;
endmodule
module DFF2(Q, D, clk, reset);
output reg Q;
input clk,reset;
input wire D;
always @(posedge clk or posedge reset)
if(reset) Q <= 1'b0;
else Q <= D;
endmodule
module DFF3(Q, D, clk, reset);
output reg Q;
input clk,reset;
input wire D;
always @(posedge clk or posedge reset)
if(reset) Q <= 1'b0;
else Q <= D;
endmodule
module DFF4(Q, D, clk, reset);
output reg Q;
input clk,reset;
input wire D;
always @(posedge clk or posedge reset)
if(reset) Q <= 1'b0;
else Q <= D;
endmodule
module direction(Q, D, clk, reset);
output reg Q;
input clk, reset;
input wire D;
always @(posedge clk or posedge reset)
if(reset) Q <= 0;
else Q <= D;
endmodule
module ms(missionary_curr, cannibal_curr, direction, missionary_next, cannibal_next);
//I/O declaration
input[1:0]missionary_curr;
input[1:0]cannibal_curr;
input direction;
output[1:0]missionary_next;
output[1:0]cannibal_next;
//inner net definition
wire bc, ncnd, nbnce, cdne, nab, ane, acd, nce,ad,
nbnc,dne,anb,cne,ncnde,ndne,cd,nabc,anbd;
//primitive logic gate instantiation
and (bc, missionary_curr[0],cannibal_curr[1]);//2-input and gate
and (ncnd, ~cannibal_curr[1], ~cannibal_curr[0]);//2-input and gate
and (nbnce, ~missionary_curr[0],~cannibal_curr[1], direction);//3-input and gate
and (cdne, cannibal_curr[1], cannibal_curr[0], ~direction);//3-input and gate
and (nab, ~missionary_curr[1], missionary_curr[0]);//2-input and gate
and (ane, missionary_curr[1], ~direction);//2-input and gate
and (acd, missionary_curr[1], cannibal_curr[1], cannibal_curr[0]);//3-input and gate
and (nce, ~cannibal_curr[1], direction);//2-input and gate
and (ad, missionary_curr[1], cannibal_curr[0]);//2-input and gate
or w(missionary_next[1],bc, ncnd, nbnce, cdne, nab,ane,acd); //7-input and gate
or x(missionary_next[0],bc, ncnd, nce, cdne, ane, ad);//6-input and gate
//y
and (nbnc, ~missionary_curr[0], ~cannibal_curr[1]);//2-input and gate
and (dne, cannibal_curr[0], ~direction);//2-input and gate
and (anb, missionary_curr[1], ~missionary_curr[0]);//2-input and gate
and (cne, cannibal_curr[1], ~direction);//-input and gate
and (ncnde, ~cannibal_curr[1], ~cannibal_curr[0], direction);//3-input and gate
or y(cannibal_next[1],nbnc, dne, anb, cne, nab, ncnde);//6-input and gate
//z
and (ndne, ~cannibal_curr[0], ~direction);//2-input and gate
and (cd, cannibal_curr[1], cannibal_curr[0]);//2-input and gate
and (nabc, ~missionary_curr[1], missionary_curr[0], cannibal_curr[1]);//3-input and gate
and (anbd, missionary_curr[1], ~missionary_curr[0], cannibal_curr[0]);//3-input and gate
or z(cannibal_next[0], ndne, nce, cd, nabc, anbd);//5-input and gate
endmodule
module test_bench();
reg [1:0]missionary_curr;
reg[1:0]cannibal_curr;
reg direction;
wire[1:0]missionary_next;
wire[1:0]cannibal_next;
ms m1(missionary_curr, cannibal_curr, direction, missionary_next, cannibal_next);
initial
begin
#2 missionary_curr=3;cannibal_curr=3;direction=1; //first is 3 missionaries and 3 cannibals with boat direction going right//
#2 missionary_curr=3;cannibal_curr=1;direction=0;
#2 missionary_curr=3;cannibal_curr=2;direction=1;
#2 missionary_curr=3;cannibal_curr=0;direction=0;
#2 missionary_curr=3;cannibal_curr=1;direction=1;
#2 missionary_curr=1;cannibal_curr=1;direction=0;
#2 missionary_curr=2;cannibal_curr=2;direction=1;
#2 missionary_curr=0;cannibal_curr=2;direction=0;
#2 missionary_curr=0;cannibal_curr=3;direction=1;
#2 missionary_curr=0;cannibal_curr=1;direction=0;
#2 missionary_curr=0;cannibal_curr=2;direction=1;
#2 missionary_curr=0;cannibal_curr=0;direction=0;//Lastly, the current state will have 0 missionary and 0 cannibal//
end
endmodule